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Surya Technologies currently offers a powerful and broad-based static analysis, verification and optimization tool suite known as SDATM. SDA fits easily into most cell-based design flows and includes the following major features:
- A static timing analyzer, with a built in delay calculator, which provides accuracy, ease-of-use and fast analysis. The timing analysis automatically takes into account critical deep sub-micron issues such as signal coupling.
- A static noise analyzer, which works in conjuction with the timing analyzer and exhaustively analyzes the design for crosstalk noise due to capacitive coupling. The noise analysis includes noise-on-delay effects due to simultaneously switching nets as well as noise induced on quiet nets due to switching aggressor nets.
- A timing optimizer, which works in conjunction with the timing analyzer and optimizes a design for both setup-time and hold-time through gate resizing and buffer insertion.
- A timing-driven design partitioner, which re-partitions a design and generates a new design hierarchy based on a detailed timing analysis, and enables a unique timing-driven physical design methodology that ensures quick timing convergence in state-of-the-art designs.
- A programmable, static design rules and constraints verifier, which can verify a wide range of critical constraints and properties. The verification covers multiple areas such as timing, coupling, electrical properties, logic functionality, and design topology/structure.
SDA uses standard input data formats (for netlists, libraries, parasitics, etc.), and includes proven links to various parasitic extractors and place-and-route tools. See SDA’s Inputs and Outputs for details.
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