Timing-driven Design Partitioning

The purpose of timing-driven design partitioning is to divide and group large amounts of logic in ways that enable a design meet critical timing constraints in a highly predictable and controllable fashion. The initial logical partitioning of a design is often not quite optimal from a physical design perspective. The logical partitioning may contain a large number of hidden timing-critical regions, which may become visible only after detailed physical design. Such problems are expensive and time-consuming to fix late in a design cycle.

Partitioning technology is designed to overcome such problems by analyzing the design early in the design cycle and producing:

• Optimal clusters (partitions) of logic in the form of separate modules, based on timing constraints.
• Intra- and inter-block constraints, including timing, wire parasitics, etc., for physical design tools such as floorplanning and place-and-route tools.

This approach enables a forward constraint-driven design flow, with reliable timing predictions early in the design cycle.  The user retains sufficient control over the cluster-generation and constraint-generation. This results in a much higher degree of controllability and predictability in the design flow, as well as an increased ability to meet physical constraints, than is possible through most other methodologies.

Based on a detailed timing analysis and certain slack calculations, SDA identifies nets that are suitable for serving as long interconnect wires. It then uses such nets to connect to the input/output pins of the newly created partitions. This reverses the normal timing closure problem, and designs the long interconnections upfront using nets that are guaranteed to have excess slack. Some of this excess slack will then get used in the wire delay (and the delay of the associated driver, etc.) when that net is actually routed later in the physical design according to SDA’s constraints for that net.

Given a large design consisting of hard macros (i.e., blocks such as memory arrays which may already have a detailed layout), datapath blocks and control/random logic, the user has the option of controlling the partitioning process by providing the following specifications:

• Identify hard blocks, custom/structured datapath blocks and pad input/output logic blocks, which should not be part of any newly created partitions.
• Specify minimum and maximum sizes of a partition. The sizes may be in terms of number of cells or other area metric.
• Specify wire-load model for the typical cluster (partition) size.
• Specify slack thresholds to be used for guiding the partitioning algorithm.
• Specify overall timing constraints for the design (clock cycle times and timing properties at primary inputs/outputs).

Based on these specifications, the portion of the design that can be subjected to the partitioning algorithm is all of the logic that does not belong to any of the non-partionable regions. This typically consists of all of the control and random logic in the design, as well as any non-structured datapath logic that is being implemented through standard logic synthesis and place-and-route.

In addition to the user specifications, SDA’s partitioning process uses the following standard inputs:

• Hierarchical Verilog gate-level netlist.
• Cell timing/functional libraries, including wire-load models.
• Extracted parasistics (DSPF) for internal nets of certain non-partitionable blocks.

After partitioning, SDA produces the following outputs:

• Verilog netlist with a modified hierarchy.
• Input/output timing constraints (arrival and required times) for each partition.
• Wire constraints (maximum delay or parasitics) for the interconnect wire at each output pin of a cluster or block.

All of the partitionable logic must be synthesized using a single wire-load model for the partition size. This wire-load model is the same as the one used by SDA for the partitionable logic. SDA reads in the synthesized gate-level netlist of the design and performs partitioning and constraint generation. It is very important that multiple partitioning solutions be explored at this stage. This implies running SDA multiple times with different constraints, so that the best overall solution may be selected prior to physical design.

After a feasible partitioning solution has been generated by SDA and selected/approved by the user, the physical design process starts. The physical design includes top-level floorplanning, block/cluster placement, pin assignment, inter-block/cluster routing, and detailed intra-cluster place-and-route. There may be iterations between place-and-route and top-level pin assignment/routing.

Partitioning may be performed at the full-chip level (datapath and other non-partitionable parts of the design can be excluded easily), or within a large functional unit/module. At either level, a decision has to be made as to how the partitioned design (chip or module) will be implemented physically. There are basically two different methods of approaching the physical design problem:

• The “hard” approach: Develop a floorplan of the partitioned logic, perform block placement for the clusters, pin assignment, etc., and then detailed place-and-route within each block (cluster).
• The “soft” approach (especially useful if partitioning has been done within a functional module): Directly perform detailed place-and-route within the functional module, with the clustering information used to group each cluster into a soft region. This could still accomplish most of the goals of partitioning, but without the extra effort required in the “hard” approach.