Static Timing Analysis, Verification and Optimization

SDA’s static timing analysis option offers a wide range of features to support accurate and efficient timing analysis of current and next generation designs, including:

• Fast and efficient analysis of very large designs.
• Easy to set up and use.
• Handles multiple phase and multiple frequency clocks.
• Handles latch-based designs, including latch transparency issues.
• Includes a built-in delay calculator, which can compute accurate cell delays and interconnect delays.
• Reads interconnect parasitic RC data (in DSPF format) in flat or hierarchical forms, and supports “feed through” and “split” module ports in hierarchical DSPF.
• Includes automatic handling of signal coupling, wherever the DSPF parasitic data includes coupling capacitors between signal nets. This significantly increases the accuracy without sacrificing efficiency.
• Efficiently analyzes real and apparent loops in the design, including combinational and latch loops.
• Supports user-specified false paths and multi-cycle paths. Further, false paths can be qualified by general timing constraints, for increased robustness in false path removal.
• False paths can be validated using design functionality, under the static design rules verification option.
• Supports logic value specification and automatic propagation for additional false-path blocking.
• Supports general timing constraint specification through SDF constraint annotation.
• Provides a range of reporting options, including critical paths, point-to-point delays, slacks and histograms.
• Outputs accurate SDF delays for use in other analysis and simulation tools.
• Generates spice decks for selected critical paths, which include all the interconnect parasitic data and loading. The critical paths are automatically sensitized statically, for easily running the simulations.
• Provides a powerful option to automatically optimize gate sizes and insert buffers to fix both setup and hold violations with accurate post-route parasitic information. Generates “ECO” information for use in incremental place-and-route changes.
• Generates accurate pin-to-pin timing models for any module or design.
• Includes various logic extraction and netlist reduction technologies to efficiently and accurately analyze large, multimillion gate designs.
• Includes an application-programming interface (API) for easily linking SDA with other software systems such as logic synthesis tools, place-and-route tools, etc.
• Supports incremental timing analysis, when design changes are provided through the API.