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Summary
Experience
Education
Publications
Patents
Contact Info
Summary
- Primary areas of interest and expertise: Modeling, simulation, analysis and optimization of technological, business, economic and natural systems, using custom-developed software and off-the-shelf software tools.
- Specific application domains with extensive experience and expertise:
- Environmental performance analysis and optimization: including supply chain energy-use and carbon emissions, freight transport emissions, and carbon footprints of products/services.
- Electronic design automation: timing analysis, noise analysis, static analysis techniques.
- 23 years of broad experience in the design and development of leading-edge computer software and hardware products, as well as in project leadership.
- Includes 12 years operating a small business providing innovative electronic design automation (EDA) software to the semiconductor industry, for modeling, analysis and simulation applications such as timing analysis, noise analysis and timing optimization.
- Experienced in a variety of programming languages and simulation software.
- Master’s degree in electrical and computer engineering. Graduate certificate in computer modeling and simulation.
- Extensive technical and freelance publications, and two patents.
Experience
- 9/95 - present: President & Principal Engineer, Surya Technologies, Inc., Portland, OR
- 1/06 - present: Modeling, simulation, and optimization software and services
- 9/95 – present: Electronic Design Automation (EDA) software
- Providing state-of-the-art EDA software for modeling, analysis, simulation, optimization and verification of large integrated circuit designs. Previously based in Silicon Valley for many years; based in Portland, Oregon, since July 2004.
- Software tools and technologies delivered to customers include: timing analyzer, design rules/constraints verifier, signal coupling and noise analyzer, timing optimizer, and timing-driven design partitioner.
- Programming languages and platforms used for software development: C, C++, Yacc, Lex, Perl, UNIX, Linux.
- Key customers in the US and Japan: Advanced Micro Devices, Equator Technologies, C-Cube Microsystems, Seiko Instruments, 3Dfx Interactive, Fujitsu Microelectronics, CadMOS Design Technology (now part of Cadence), Procket Networks, ReShape, SII EDA Technologies, Atrenta, and JEDAT Innovation.
- 6/91 - 8/95: Member of Technical Staff & Project Leader, Silicon Graphics, Mountain View, CA
- Led a software R&D team in the development of a new gate-and-transistor-level static timing verifier that includes a number of innovative features. Developed detailed timing models for electronic circuits at the transistor and gate levels. Directed and participated in a 2-year software development project. This tool has been used to analyze/verify large standard-cell and custom integrated circuit designs.
- Led a hardware design team in the development of a high-bandwidth memory subsystem for SGI’s Challenge multiprocessor server systems. Responsible for two large ASICs and complex system design. Also, developed CAD methodology and tools to support/enhance testability, timing analysis and design rule checking. Received a US patent for part of this work.
- 6/89 - 6/91: Member of Technical Staff, Sun Microsystems, Mountain View, CA
- Designed a secondary cache-controller chip for Sun’s SuperSparc microprocessor. Also, designed the scan/JTAG test logic for the chip. Contributed to CAD methodology including timing analysis, synthesis and circuit verification. Received a US patent for part of this work.
- 3/88 - 6/89: Senior Design Engineer, Intel Corp., Santa Clara, CA
- Member of the 486 microprocessor design team. Responsible for processor architecture issues, microcode development, architecture/microcode verification, and verification tools.
- 3/85 - 3/88: Systems Engineer, Reflectone Inc., Tampa, FL
- 6/84 - 2/85: Design Engineer, Dynamic Computer Architecture, St. Petersburg, FL
Education
- 1/05 – 3/06: Portland State University, Portland, OR
- Graduate Certificate in Computer Modeling and Simulation. Focus: System dynamics, discrete-event simulation, agent-based simulation, optimization, and statistical analysis. Used software tools such as Vensim, Arena, NetLogo, and MATLAB. GPA: 4.0.
- 1/99 – 12/99: University of California, Berkeley, CA
- Undergraduate and graduate courses in the natural sciences. Focus: Biology, biochemistry and ecology. Grades: A’s.
- 9/88 – 3/90: Stanford University, Stanford, CA
- Graduate courses in electrical/computer engineering. Focus: VLSI design and parallel computer architectures. Grades: A’s.
- 8/85 – 12/87: University of South Florida, Tampa, FL
- Graduate courses in electrical engineering. Focus: Digital communication systems and digital signal processing. GPA: 4.0.
- 1/83 – 8/84: University of Texas, El Paso, TX
- 7/77 – 5/82: University of Madras, India
- BS in Electrical Engineering. Grade: Honors.
Publications
- Conference/Journal Papers and Technical Articles
- “Red, White and Green: Investigating the Energy Intensity of Wine Distribution”, International Conference on Business and Sustainability, November 2007.
- “Determining the Effects of a Food Carbon Footprint Training Tool on Consumer Knowledge, Transfer Intentions, and Environmental Self-Efficacy”, International Conference on Business and Sustainability, November 2007.
- “Balancing Carbon Emissions and Conviviality in Local Food Supply Networks”, International Conference on Business and Sustainability, November 2007.
- “Greening the Supply Chain: Improving Carbon Emissions in the Distribution of Food and Beverages”, INFORMS Annual Meeting, November 2007.
- “Analyzing and Optimizing the Environmental Performance of Supply Chains”, ACEEE Summer Study on Energy Efficiency in Industry, July 2007.
- “Enhancing the Environmental Performance of Supply Chains”, in Positive Development: from vicious circles to virtuous cycles by J. Birkeland, 2007.
- “An Agent-Based Model of Trade with Distance-Based Transaction Cost”, Summer Computer Simulation Conference, July 2006.
- “Is Lean Necessarily Green?”, 50th Annual Meeting of the International Society for the Systems Sciences, July 2006.
- “Emergence of Networks in Distance-Constrained Trade”, InterJournal & International Conference on Complex Systems, June 2006.
- “Using Simulation to Understand and Optimize a Lean Service Process”, Spring Simulation MultiConference, April 2006.
- “Digital Divide and Poverty”, Journal of Poverty, Vol. 5, Issue 4, 2001.
- “Timing Verification of Dynamic Circuits”, IEEE Journal of Solid-state Circuits, Vol. 31, Issue 3, March 1996.
- “Timing Verification of Dynamic Circuits”, Custom Integrated Circuits Conference, May 1995.
- “Follow these guidelines to design testable ASICs, boards and systems”, EDN, August 19, 1993.
- “Generalized Delay Optimization of Resistive Interconnections Through an Extension of Logical Effort”, IEEE International Symposium on Circuits and Systems, May 1993.
- “A Structured Design for Test Methodology”, 11th IEEE VLSI Test Symposium, April 1993.
- “ATPG tools are a varied lot”, Electronic Engineering Times, September 21, 1992.
- “Analysis of Ring, Cube and Tree Multimicrocomputer Systems”, IEEE Region 5 Conference, April 1986.
- “A Monitor for a Dynamic Multicomputer System”, First International Conference on Supercomputing Systems, December 1985.
- Freelance Writings
- Recent Presentations
Patents
Contact Information
- Phone: 503-260-9861
- E-mail: venkat-contact at suryatech.com
- Address: 4888 NW Bethany Blvd., Suite K5, #191, Portland, Oregon 97229, USA
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